                              Release Notes
                              =============

                           Broadcom Bootcode Firmware 
                                    For 
                             BCM5717 and BCM5718                                 

                 Copyright (c) 2009-2015 Broadcom Corporation
                          All rights reserved.


-------------------------------
Version 1.65 - June 5, 2015   
-------------------------------

   Fixes:
   ======
   1.  Problem: CASE#923947
       The SPI clock (i.e. SCLK) runs twice speed 
       faster than the default on some OEM platforms.

       Cause:
       The function, which handles the VPD event, 
       accidentally clears the register offset 0x7014 
       Bit [7] that changes SPI_CLK_DIV.

       Fix:
       Fixed the function in question and resolved the issue.

-------------------------------
Version 1.64 - April 8, 2015   
-------------------------------

   Enhancement:
   ============		                         
   1. (JIRA) (CTRL-20518) 909424: Bootcode version update

-------------------------------
Version 1.63 - November 19, 2014   
-------------------------------

   Fixes:
   ======
   1. Problem: CQ74011
      Share memory offsets overwritten due to a change in a 
      common header file between bootcode and PM Offload firmware.

      Cause:
      Changes made to this common header intended for PM offload 
      firmware inadvertently overwrites certain offset in share 
      memory for bootcodes compiled with this header file.
     
      Fix:
      fix affected header file and re-release all affected bootcodes.
    
-------------------------------
Version 1.62 - October 24, 2014   
-------------------------------

   Enhancement:
   ============		                         
   1. CQ73784.  NX1 NVRAM L0s & L1s NVRAM entries to match NX2 designs.
      Two NVRAM bits are defined to control ASPM support.
    
--------------------------------
Version 1.61 - August 13, 2014
--------------------------------    
   Fixes:
   ======
   1. Problem: CQ73687 
	  Device link at 100M in OOB mode when the WoL in NVRAM is disabled
     
      Cause:
      The issue was due to the feature_configb was not copied to local 
	  variable which controls the link. 
     
      Change:
      Copying feature_configb to local variable resolved the issue.
	                
------------------------------
Version 1.60 - July 11, 2014
------------------------------    
   Enhancement:
   ============		
   1. CQ73664: 5718 bootcode version up to 1.60 for OEM.
	  
   Note:
   ============		
   1. This release is for 5718 only.

------------------------------
Version 1.59 - October 10, 2013
------------------------------    
   Enhancement:
   ============		
   1. CQ71212: Adding a NVRAM Control bit (offset 0x21C[1]) to enable/disable 
      AutoNeg 1G half duplex advertisement.
	  
--------------------------------
Version 1.58 - February 22, 2013
--------------------------------    
   Fixes:
   ======
   1. Problem: 
      Bootcode copied invalid PHY ID to shared memory.

      Cause:
      After reset, Bootcode reads PHY ID and copies it to shared memory without
      checking whether the GPHY is still in the power down state. As a result,
      the invalid PHY ID may be copied to the shared memory.
     
      Change:
      Bootcode will power up the GPHY when reading the PHY ID.
                          
-------------------------------
Version 1.57 - January 23, 2013
-------------------------------    
   Fixes:
   ======
   1. Problem: CQ67387
      PCIe Gen2 (-3.5dB) Tx Template failure

      Cause:
      The default PCIe Gen2 Transmitter amplitude is not preserved. Bootcode
      overwrites the PCIe Gen2 Transmitter amplitude when programming
      PCIe Tx De-Emphasis.
     
      Change:
      Bootcode will preserve the PCIe Gen2 Transmitter amplitude to resolve
      this issue.

   2. Problem: CQ67388
      PCIe Tx de-emphasis for Gen2

      Cause:
      In b57diag secfg #68 configuration controls the PCIe Tx de-empahsis for
      both Gen1 and Gen2. It's suggested to differentiate this option between
      Gen1 and Gen2 for better clarification.
     
      Change:
      Using the existing defined control bits to control the PCIe
      Tx de-empahsis for Gen1.  Defined two more control bits in NVRAM to
      control the PCIe Tx de-empahsis for Gen2. The default setting is -3.5dB
      for Gen1 and -6dB for Gen2.
      
   3. Problem: CQ67153
      Ethernet link down on one port causes throughput reduction on second
      port.

      Cause:
      "Link Idle Mode" on Ethernet link down port causes throughput reduction
      on other port.
     
      Change:
      Disable Link Idel Mode feature on both ports. 

   4. Problem: CQ67271
      NETBIOS name query and TCP SYN v4/v6 does not work when PM Offload
      enabled.

      Cause:
      Bootcode does not restore the last_driver_state in the shared memory
      which cause PM Offload FW not to run.
     
      Change:
      Bootcode restores the last_driver_state to resolve this issue. 

      
------------------------------
Version 1.56 - January 4, 2013
------------------------------    
   Fixes:
   ======
   1. Problem: CQ67153
      Ethernet link down on one port causes throughput reduction on second
      port.

      Cause:
      "Link Idle Mode" on Ethernet link down port causes throughput reduction
      on other port.
     
      Change:
      Disable Link Idel Mode on both ports.

      
   Enhancement:
   ============		
   1. Enable/Disable PXE in Phase 1 Bootcode.       
   2. Preserve the configuration data in shared memory in Phase 2 BC since
      BC can no longer be able to read these data after driver enabled
      Interesting packet WOL (0x400[19] = 1).
       
-----------------------------
Version 1.55 - April 24, 2012
-----------------------------

   Fixes:
   ======
   1. Problem: CQ62817
      NVRAM secfg #68 PCIe Tx De-Emphasis option does not take effect.
	  
      Cause:
      NVRAM secfg #68 PCIe Tx De-Emphasis option does not support PCIe Gen 2.

      Change:
      Added PCIe Gen 2 Tx De-Emphasis support.
                                                        
-----------------------------
Version 1.54 - April 12, 2012 
-----------------------------    

   Fixes:
   ======
   1. Problem: CQ62448
      Incorrect Device ID during the system cold boot test in particular OEM
      platforms.
	  
      Cause:
      Bootcode does not load fast enough to program the  Device ID in these
      OEM platforms.

      Change:
      Rearrange the Bootcode to take advantage of the Fastboot feature in
      order to achieve a faster loading.
   
   2. Problem: CQ62382
      NCSI will not work after a certain cycles of AC on/off
	  
      Change:
      Bootcode will kick start NCSI FW if NCSI FW is not loading.
      
-----------------------------
Version 1.53 - March 08, 2012 
-----------------------------    

   Enhancement:
   ============		
   1. Bootcode will copy func_mode information to RxCPU and APE Shared Memory
      for drivers and APE FW after the device is out from reset and when
      Vmain is present.
                                                          
-----------------------------
Version 1.52 - March 05, 2012 
-----------------------------    

   Enhancement:
   ============		
   1. Bootcode copy func_mode information to RxCPU and APE Shared Memory for
      drivers and APE FW.  Bootcode  will poll pcie register 0x408 bit 7 for
      first config done to determine whether the device is out from reset. 
      
--------------------------------
Version 1.51 - February 18, 2012 
--------------------------------                 

   Fixes:
   ======
   1. Problem: CQ61631
      ESX 4.1: Passthrough- can not pass traffic on any Redhat 6.X vm hosts
      in passthrough mode.
	  
      Cause:
      The MSIX interrupt is not getting setup properly by ESX pass-thru
      module. ESX 4.1 pass-thru module can't not read the MSIX table properly
      if MSIX table offset and PBA table offset are not page aligned.

      Change:
      Change the Boot code to setup both MSIX table offset and PBA table 
      offset to page aligned for 5718.
   
---------------------------------
Version 1.50 - February  13, 2012
---------------------------------

   Enhancements:
   =============
   1. CQ61567: Enabling alternate clock source via Reg 0x3624 and 0x3628 for
      specific OEM.
	  						  
--------------------------------
Version 1.49 - December 29, 2011 
--------------------------------

   Fixes:
   ======
   1. Problem: 
      The LED remains on after DOS ungraceful shutdown when WOL is disabled. 
	  
      Cause:
      The root cause is that BC cannot successfully power down the unused
      GPHY. BC powered down unused GPHY by read/modify/write mii reg 0x00 to
      set GMII_CONTROL_ISOLATE bit and GMII_CONTROL_POWER_DOWN bit. When BC
      write back to mii reg 0x0, the MII_CONTROL_AUTONEG_ENA bit is still set
      which keeps the GPHY LED remain on.

      Change:
      Modified BC not to read/modify/write when updating mii reg 0x00. BC will
      only write GMII_CONTROL_ISOLATE bit and GMII_CONTROL_POWER_DOWN bit to
      mii reg 0x00 to completely power down the unused GPHY.
	  
--------------------------------
Version 1.48 - December 14, 2011 
--------------------------------

   Fixes:
   ======
   1. Problem: 
      BC failed to identify OEM in CQ60296. 

      Cause:
      Incorrect NVRAM offset was used to get OEM information. 
      
      Change:
      Using correct NVRAM offset when gathering OEM information to resolve the
      issue.

   
--------------------------------
Version 1.47 - December 12, 2011 
--------------------------------

   Enhancements:
   =============
   1. CQ60296: Power Down Unused Gen2 PCIe Lanes for specific OEM.
   
--------------------------------
Version 1.46 - November 15, 2011 
--------------------------------

   Enhancements:
   =============
   1. Set the default NVRAM settings for the Network SerDes TX Amplitude 
      and Pre-emphasis to be closer to the HW default as possible. 
      The fiber mode output voltage measurements are closest to the HW 
      default when the TxAmpl/TxPre configuration is 01/00.
      This common default applies to both fiber and SGMII modes.
	  
   Notes
   =====
   1. This release is for 5718 only.	  
	 

--------------------------------
Version 1.45 - November 14, 2011 
--------------------------------

   Enhancements:
   =============
   1. CQ 59110 - Provide the access to Network SerDes adjustment parameter in
      5718. Defined 4 control bits to adjust Network SerDes TX Amplitude and
      Pre-emphasis.
	  
   Notes
   =====
   1. This release is for 5718 only.	
	  
--------------------------------
Version 1.44 - November 10, 2011 
--------------------------------

   Enhancements:
   =============
   1. CQ 59624. Removed V1.41 changes. BC set BIT 12 and BIT 11 of Reg 0x40C
      to 11b in LINK/ACTIVITY LED Mode and SPEED10/100 LED Mode.
   						  
---------------------------------
Version 1.43 - September 21, 2011 
---------------------------------

   Fixes:
   ======
   1. Problem: 
      Get version ID command in NCSI FW does not return correct IDs. 

      Cause:
      BC copy the svid and ssid to the APE shared memory. The get version ID 
      command in NCSI FW will read the IDs from here. Each port has its own
      svid and ssid stored in the NVRAM and each port has its own space in APE
      shared memory to store these IDs. However BC only copy the svid and ssid
      of port 0 from NVRAM offset to the APE shared memory for all ports. 
      
      Change:
      BC will copy the port svid and ssid to its own space of the APE shared
      memory.
	  
---------------------------------
Version 1.42 - September 09, 2011 
---------------------------------

   Enhancement:
   ============		
   1. CQ 56671: OEM requested to have OS control ASPM. Modified BC to
      advertise only L1 ASPM in any future 5718/17 Bootcode to work with OEM's
      request.
	  
------------------------------
Version 1.41 - August 26, 2011 
------------------------------

   Fixes:
   ======
   1. Problem: 
      BC set BIT 12 and BIT 11 of Reg 0x40C to 1 in LINK/ACTIVITY LED Mode and
      SPEED10/100 LED Mode.

      Change:
      Follow the Register Spec to set BIT 12 and BIT 11 to 0 in both modes.

						  
----------------------------
Version 1.40 - July 22, 2011 
----------------------------

   Fixes:
   ======
   1. Problem: 
      In Func_mode support, BC may run into a infinite loop when detecting
      whether the device has come out from reset if the device states in
      reset.

      Change:
      Modify BC to poll for a finite number of times to avoid a dead lock
      situation.
	  						  
----------------------------
Version 1.39 - July 20, 2011 
----------------------------

   Fixes:
   ======
   1. Problem: 
      Func_mode information in Shared Memory get clear after reset.
	
      Change:
      A debug code overwrites the func_mode information in Shared Memory.
      Remove the debug code to resolve the issue.
	  
----------------------------
Version 1.38 - July 12, 2011   
----------------------------
   Enhancement:
   ============		
   1. BC copy func_mode information to RxCPU and APE Shared Memory for drivers
      and APE FW.  A signature (0x362c) has been introduced for the func_mode
      information validation.  Driver and APE FW should validate the func_mode
      information in the shared memory by checking this signature.
	  
----------------------------
Version 1.37 - July 06, 2011   
----------------------------
   Enhancement:
   ============		
   1. BC copy func_mode information to RxCPU and APE Shared Memory for drivers
      and APE FW.
	  
----------------------------
Version 1.36 - June 20, 2011   
----------------------------
   Enhancement:
   ============
   1. Modified OS absent mode EEE script to improve the link stability.  	  
 
   2. Modified BC to continue monitoring the link status after entering Vaux
      only mode.
   
   3. Moved the phase 1 BC starting address in scratch pad to 0x8003400 to
      increase code space.
   
---------------------------
Version 1.35 - May 18, 2011   
---------------------------

   Enhancement:
   ============
   1. Update OS absent mode EEE script. The OS absent mode EEE support is
      disabled by default in NVRAM.
	  
   2. BC will set Reg 0x1804[3] to fully powerdown unused lanes when in Gen2
      mode.
   
--------------------------
Version 1.34 - May 4, 2011   
--------------------------
   Fixes:
   ======
   1. Problem: CQ54582
      Device disappears during reboot test in OEM System

      Cause:
      The Serdes Register 18 in Block Address 801 is corrupted with a value of
      0x2070 which will reset the PLL and power down its PLL and PCIE
      Reference Clock Buffer when the PCIE Serdes PIPE Interface transition
      from P2 to P1 while the system is resuming from sleep state to Wake
      State. The Serdes Register 18 in Block Address 801 corruption occurs
      because the rising edge of the PERST_L signal is de-asserted in the
      middle of a MDIO transaction.

      Change:
      Update the bootcode to perform a back to back write of the MDIO Access
      with the same Block Address whenever bootcode is programming the PCIE
      Serdes Register.
	
-----------------------------
Version 1.33 - April 15, 2011   
-----------------------------

   Enhancement:
   ============
   1. CQ 54515: Disable EEE by default in Boot Code. Set the default state of
      the EEE_Enable bit in NVRAM to disable.
	  
-----------------------------
Version 1.32 - March 28, 2011   
-----------------------------

   Enhancement:
   ============
   1. CQ 53468.  Adding Single Bit ECC Error Correction support.
      Defined Bit 2 of Extended Configuration in NVRAM to control 
      whether the chip will generate GRC reset upon detection of ECC error.  

--------------------------------
Version 1.31 - February 25, 2011
--------------------------------
	  
   Enhancement:
   ============
   1. CQ 53107 - Force Expansion ROM Advertisement Configuration.
      Defined Extended Configuration for each port started at NVRAM offset
      0x278. BIT_1 of Extended Configuration is defined as Force Expansion 
      ROM Advertisement Enable. BC will enable/disable Expansion ROM
      Advertisement based on the state of the Force Expansion ROM
      Advertisement Enable bit after reset. BC will copy Extended
      Configuration to RxCPU Shared Memory offset 0xdf8 and APE RxCPU Shared
      Memory.
	  
   2. Reducing the link status polling frequency to every 1s when EEE is
      enabled.
   
--------------------------------
Version 1.30 - February 14, 2011   
--------------------------------

   Fixes:
   ======
   1. Problem: 
      BC does not enable EEE at 100M.

      Cause:
      EEE enable logic fails to enable EEE at 100M.
      
      Change:
      Modify the EEE enable logic to resolve the issue.
	  
--------------------------------
Version 1.29 - February 11, 2011   
--------------------------------

   Fixes:
   ======
   1. Problem: 
      BC enabled LPI with non-EEE link partner.

      Cause: 
      There is an issue in the original EEE enable script. One of the checking
      conditions in this EEE enable script will fall through even with link
      partner is not supporting EEE. As a result the BC will enable LPI even
      with non-EEE link partners.
      
      Change:
      Modify the EEE enable logic in the script to resolve the issue.
   
--------------------------------
 Version 1.28 - January 19, 2011 
--------------------------------
   Fixes:
   ======
   1. Problem: 
      Port1 BC is accessing Port0 Mutex in EEE routine.

      Cause:
      BC did not identify the Port before requesting and releasing Mutex in
      EEE routine.
		
      Change:
      BC will identify the Port first before requesting and releasing Mutex in
      EEE routine.

--------------------------------
 Version 1.27 - January 12, 2011 
--------------------------------
   
   Enhancement:
   ============
   1. Enabled Link Idle Mode for 5717 B0 and 5718 B0.
   
   2. CQ50170. Adding new VPD data entry to BC image.
	  
--------------------------------
 Version 1.26 - January 07, 2011 
--------------------------------
   Fixes:
   ======
   1. Problem: CQ52007
      New EEE configuration in NVRAM for BC for Cotopaxi

      Change:
      Using Bit 13 of HW_CONFIG instead of Bit 27 of Feature_Config to
      enable/disable EEE. B57diag V14.23 or later will support this change. 

   Enhancement:
   ============
   1. Adding Dual SDID per port support.  Dual SDID per port will be stored in
      NVRAM starting from 0x22C.
	  
   2. BC will drive GPIO2 to low to avoid power glitch during Vaux to Vmain
      transition.

   3. BC will copy feature_config and HW_config from RxCPU shared memory to
      APE shared memory after reset.         
	  
   4. Enabled APE Heartbeat Monitoring function to monitor the heartbeat of
      APE in Vaux mode as well.
   
   Note:
   =====
   1. From this version and on, the BC memory layout of this project will be 
      switched to be the same as in 5719 and 5720. B57diag V14.23 or later
      will support this new change.

--------------------------------
 Version 1.25 - December 2, 2010 
--------------------------------
   Enhancement:
   ============
   1. Adding NVRAM control bit to control enabling and disabling EEE support
      in OS absent mode. The default setting is enable.
	  
   2. Updating the Virtual Mac Support. Bootcode will use the Virtual Mac
      Address if Virtual Mac is enabled. Otherwise, Mac Address will be taken
      from NVRAM.
	  
   3. Adding NVRAM control bit to control PCIe Tx De-emphasis Configuration. 
	  
--------------------------------
 Version 1.24 - October 27, 2010 
--------------------------------


   Enhancement:
   ============
   1. Enabling EEE support in OS absent mode.

--------------------------------
 Version 1.23 - October 21, 2010 
--------------------------------


   Fixes:
   ======
   1. Problem: 
      Slow access to the VPD data in NVRAM.
 
      Cause:
      The NVRAM clock is slowed down by the CPMU .  
      
      Change:
      BC will speed up the NVRAM clock when accessing VPD data 
      in NVRAM then slow down the clock when accessing is completed. 

---------------------------------
 Version 1.22 - September 1, 2010 
---------------------------------


   Fixes:
   ======
   1. Problem: 
      Device Class Code is erased by BC.
 
      Cause:
      When updating the ASIC Revision at PCI-E Reg 0x8, BC unexpectedly 
      erased the Device Class Code at Reg 0x9.  
      
      Change:
      BC will preserve the Device Class Code at Reg 0x9 when updating the
      the ASIC Revision at PCI-E Reg 0x8


-------------------------------
 Version 1.21 - August 31, 2010 
-------------------------------


   Enhancement:
   ============
   1. Added support to store VPD data in using directory method.

   2. Update PCIE Reg 0x8 with asic revision. 

   3. Complete Phase 1 bootcode before powering down the port in play dead
      mode.

   4. Do not power down the Phy port when NCIS is enabled in play dead mode.


-----------------------------
 Version 1.20 - July 26, 2010 
-----------------------------

   Enhancement:
   ============
   1. Added APE Heartbeat Monitoring function to monitor the heartbeat of APE.  
      In case the heartbeat is not updating for a few cycles, Bootcode will 
      reset APE. Before APE reset, bootcode will update RxCPU_RESET_APE_COUNT 
      and copy APE_STATE register to RxCPU_LAST_APE_STAT and 
      APE_SHMEM_APE_FW_STATUS_ADDR to APE_SHMEM_RXCPU_LAST_APE_FW_STAT in APE 
      shared memory. The APE Heartbeat Monitoring function will be disabled if 
      the APE heartbeat interval at offset 0x24 in APE shared memory is zero.
      In addition, the monitoring period will be defaulted to 6.2 sec if the 
      APE heartbeat interval is too short.  This function is enabled or
      disabled by Bit_0 of APE_FW_BEHAVIOR.


-----------------------------
 Version 1.19 - July 15, 2010 
-----------------------------
 
   Fixes:
   ======
   1. Problem: CQ48144
      5718 unable wake up when WOL is only enabled in Driver.
 
      Cause:
      When driver enable WOL on only one port and the WOL Enable bits are not
      set in NVROM of both ports,  the Bootcode of the WOL disabled 
      port will power down the device since it does not aware of WOL is
      enabled on the other port. 
      
      Change:
      BC of the WOL disabled port will HALT RxCPU and power down the 
      GPHY instead of IDDQ the device on the way down.  

   Enhancement:
   ============
   1. Only set Mac Port Mode after Bootcode reset the GPhy.  Bootcode will not 
      reset the Gphy if driver is present. 

--------------------------------------------
 Version 1.18 - June 07, 2010 
--------------------------------------------
 
   Enhancement:
   ============
   1. Updated the serdes powerdown script for Port 0.

   2. Enable Function Level Reset by default.

   3. Set Bit 10 and Bit 11 of MII Register 0x0 to power down Gphy.

--------------------------------------------
 Version 1.17 - May 10, 2010 
--------------------------------------------
 
   Enhancement:
   ============
   1. Adding Function Mode support.  Bootcode will enable and disable port
      based on func_mode[2:0] input pins which are controlled by system BIOS.
      Bootcode will evaluate them after the device comes out of system reset 
      (PERST_L) and perform necessary tasks to safely power down disabled 
      functions. 

--------------------------------------------
 Version 1.16 - May 06, 2010 
--------------------------------------------
 
   Enhancement:
   ============
   1. Modified the initializing and enabling ECC protection against
      data corruption in RxMbuf, TxMbuf and BD SRAM. And removed 
      ECC coverage for RXCPU Shared Memory.

--------------------------------------------
 Version 1.15 - May 03, 2010 
--------------------------------------------
 
   Enhancement:
   ============
   1. Initializing and enabling ECC protection against
      data corruption in Shared Memory, RxMbuf, TxMbuf and BD SRAM.

--------------------------------------------
 Version 1.14 - April 27, 2010 
--------------------------------------------
   Fixes:
   ======
   1. Problem: 
      Function 1 bootcode cannot write to APE shared memory.
 
      Cause:
      The access of APE Control Space, APE Shared Memory Space 
      and APE Peripheral Space from Function 1 is controlled by
      Bit 18:16 of Reg 0x70 in Function 0. 
      
      Change:
      Function 0 bootcode will set Bit 18:16 of Reg 0x70 during
      initialization to allow access of APE Control Space, APE Shared Memory
      Space and APE Peripheral Space from Function 1.

--------------------------------------------
 Version 1.13 - April 20, 2010 
--------------------------------------------
   Fixes:
   ======
   1. Problem: 
      Phase 2 Bootcode is loaded from NVRAM in every reset.
 
      Cause:
      Phase 1 Bootcode should setup the Phase 2 Fast Boot Enable bit
      according to the Phase 1 Fast Boot Enable status which is stored 
      in a variable.  However, in the current previous version the variable
      was not updated correctly. As a result, the Phase 2 Fast Boot is
      disabled and the Phase 2 Bootcode will be loaded from NVRAM upon
      every reset.
 
      Change:
      Bootcode was modified to update the variable correctly with 
      the Phase 1 Fast Boot Enable status.

   Enhancements:
   =============
   1. Make use of APE Mutex Registers when accessing MII register
      of Function 0 and Function 1.
      
   2. Set Bit 18:16 of Reg 0x70 when writing to APE Control Space,
      APE Shared Memory Space and APE Peripheral Space.

   3. Bootcode will issue an extra MII write to select Serdes Register Block
      to eliminate Serdes Register corruption.

--------------------------------------------
 Version 1.12 - April 02, 2010 
--------------------------------------------

   Enhancements:
   =============
   1. The NC-SI Packet ID support has been added.
      
   2. Bootcode will not generate APE Event since 5717/5718/5724 
      do not support APE Event.

   3. The Virtual Mac Support is added. Bootcode will use the 
      Virtual Mac Address provided by the NC-SI firmware if Virtual
      Mac is enabled.  Otherwise, Mac Address will be taken from
      NVRAM.
     
--------------------------------------------
 Version 1.11 - March 03, 2010 
--------------------------------------------

   Enhancements:
   =============
   1. Bootcode 1.11 will support 5717/5718/5724 B0.
      
   2. Bootcode will only apply the following workarounds on 5717/5718/5724 A0.
      a. Using Bit 5 of Reg 0x3664 to identify Serdes port.
      d. Powering down the PLL during Clk Req and keep ref Clk buffer powered up.
      c. Stretched the timing to 640ms
   
   3. Increased image size to 11264 bytes.
   
--------------------------------------------
 Version 1.10 - February 22, 2010 
--------------------------------------------

   Enhancements:
   =============
   1. Updated the enhancement in V1.08.  
      Bootcode will preserve Register 0x64dc, Bits [8:0] instead of Bits [3:0]
      when writing the L0s & L1 Exit Latencies. 

--------------------------------------------
 Version 1.09 - February 18, 2010 
--------------------------------------------

   Enhancements:
   =============
   1. Updated the enhancement in V1.08.  
      Bootcode will preserve Register 0x64dc, Bits [3:0] when writing the 
      L0s & L1 Exit Latencies. These Bits [3:0] determine the advertised 
      link speed (0x1 for 2.5GT/s, 0x2 for 5GT/s).

--------------------------------------------
 Version 1.08 - February 12, 2010 
--------------------------------------------

   Enhancements:
   =============
   1. Bootcode will program the L0s & L1 Exit Latency by writing 
      the reg_link_capability register at offset 0x64dc to 0xD75E11 

--------------------------------------------
 Version 1.07 - December 21, 2009 
--------------------------------------------

   Enhancements:
   =============
   1. Adding the following script to power down PLL during clock req and do
      not powered down ref clock buffer. 
      In addition, it will stretch the timing to 640ms. 
      1. mii_write(0, 0x1F,0x8010);
      2. mii_write(0, 0x19,0x0060);       
      3. Set b22 of 0x6800, and then set bits [8:5] (read/modify/write) of
         7c14.

--------------------------------------------
 Version 1.06 - December 8, 2009 
--------------------------------------------

   Fixes:
   ======
   1. Problem: CQ44492 
      Sawtooth can not get the correct PHY ID on 5717.
      
      Cause:
      Phy ID value in share memory offset 0xb74 was cleared later on. 

      Fix:
      Do not clear shared memory offset 0xb74 if it stores the Phy ID. 

----------------------------
 Version 1.05 ---- 11/09/09 
----------------------------
1. Added 5724 support

2. Enhancement:
   Make change to support management firmware can only be enabled in Port#1.

3. Problem: 
   CQ44396:
   The port2 will link down when running WOL Negative test.
   CQ44321:
   The port2 will link down when WOL=Disabled

   Cause:
   Port#1 bootcode detected APE patch code is enabled; as a result, it will
   not power the mac and the phy. Port#2 bootcode may power down the phy via
   CPMU when WOL is disabled since it cannot tell if APE patch is enabled in
   Port#1.

   Change: (Continue)
   Bootcode will not set bit_7 (ASF enabled) of shared memory at 0xD34 if it
   detects APD Patch code instead of management firmware is running.
   Bootcode will check APE_STAT_REG[31:24]. If it is 0x46, it indicates APE
   boot loader loaded APE patch code from NVRAM and patch has been applied.
   Then bootcode will not set bit_7 of shared memory at 0xD34.

----------------------------
 Version 1.04 ---- 11/04/09 
----------------------------
1. Problem: 
   CQ44396 
   The port2 will link down when running WOL Negative test.
   CQ44321:
   The port2 will link down when WOL=Disabled

   Cause:
   Port#1 bootcode detected APE patch code is enabled, as a result, it will
   not power the mac and the phy. Port#2 bootcode may power down the phy via
   CPMU when WOL is disabled since it cannot tell if APE patch is enabled in Port#1.

   Change:
   To resolve this, the bootcode will check for APE enabled bit for both ports
   before power down the phy. In addition, bootcode will clear the phy power
   down bit in the CPMU after POR or GRC reset.

----------------------------
 Version 1.03 ---- 10/29/09 
----------------------------
1. Enhancement:
     Read Reg 3664 bit 5 to detect Serdes Port.

----------------------------
 Version 1.02 ---- 10/22/09 
----------------------------
1. Problem: 
	Driver may over write driver's Port Mode setting.
   Cause:
	Bootcode will config the Port Mode setting in register 0x400 based on the link speed which may over write the setting done by driver.
   Fixed:
    Bootcode will config the Port Mode only when driver is not present.

----------------------------
 Version 1.01 ---- 10/20/09 
----------------------------
1. Problem: CQ44147
	WOL doesn't work on port0.
   Cause:
	To resolve CQ 43030, the port mode must be set to GMII in case of FPGA board.
   Fixed:
    Undo workaround for CQ 43030.


----------------------------
 Version 1.00 ---- 10/2/09 
----------------------------
1. Enhancement:
   Set PXE BAR SIZE to zero if PXE is disabled in NVRAM.

2. Problem: 
	Bootcode fail to reset and initialize the Phy in oob reset.
   Cause:
    Bootcode logic failed to detect the reset type.
   Fix:
    Fixed the logic in question.


----------------------------
 Version 0.09 ---- 9/25/09 
----------------------------
1. Enhancement:
     Set the following CPMU registers in Port 1 to fix the TLP clock control issue:
        1. write 0x3610[12:8] to 5'b1
        2. write 0x361C[12:8] to 5'b1
 
      This should cause port 1 CPMU to always frequency multiplier to drive TLP clock.


----------------------------
 Version 0.08 ---- 9/24/09 
----------------------------
1. Problem:
     Bootcode did not release Mutex after Phy access.
   Cause:
     The Mutex register offset in bootcode is incorrect.
   Fix:
     Correct the mutex register offset to resolve the issue.

2. Problem:
     Bootcode change the TLP clock setting.
   Cause:
     TLP clock is controlled by the APE clock from Port 1.
	 Bootcode slow down the APE clock and cause the TLP clock to slow down.
   Fix:
     Bootcode should not slow down the APE clock for Port 1. 

----------------------------
 Version 0.07 ---- 9/21/09 
----------------------------
1. Re-build bootcode version 0.06 for real 5717 and 5718.

----------------------------
 Version 0.06g ---- 8/7/09 
----------------------------
1. Problem: CQ 43030
	Sawtooth to do Load/unload stress test  will link down.
   Cause:
    The port mode in the mac had been set ny bootcode according to link speed.  
	In case of FPGA board, the port mode must be set to GMII.
   Fixed:
    Hard coded the port mode to GMII in g version of bootcode.

----------------------------
 Version 0.05g ---- 7/27/09 
----------------------------
1. Problem:
	v0.04g shows link down in windows though the Link LEDs show link on the boards and on the switch.
   Cause:
    The port mode in the mac had not been set up correctly.
   Fixed:
    Set up the port mode in the mac based on the link speed.  If link is down, set the port mode to GMII mode.
   
2. Problem:
    The Power Budgeting Test of SIGTest failed.
   Cause:
    The Power Budgeting Registers (0x510 to 0x518) had not been programmed with the correct value.
   Fixed:
    Program the Power Budgeting Registers with the following values will pass the test.
	reg 0x510  0x0007812c ( 4.4 watts in D0 Max)
	reg 0x514  0x00058116 ( 2.2 watts in D0 Sus)
	reg 0x518  0x0004610A  ( 1 Watt in D3AUX)

----------------------------
 Version 0.04g ---- 7/16/09 
----------------------------
1. Updated the Mutex register address.
   APE_MUTEX_REQUEST_REGISTER0		    0xC0015000
   APE_MUTEX_GRANT_REGISTER0		    0xC0015020

2. Making the selection of MSI-X vectors between 5 and 17 programmable for 5718.
   Added NVRAM control bit to select number of MSI-X vectors for 5718.

3. Rewrite the Mutex Request and Mutex Grant functions.


----------------------------
 Version 0.03g ---- 4/13/09 
----------------------------
1. Added Expansion ROM support

   Added Expansion ROM support.  
   Programmed Expansion ROM address at Reg 0x68ec. 
   Programmed Expansion ROM size at Reg 0x6408.

2. Added VPD read support

   Bootcode will return the VPD data stored at NVRAM when VPD read request is detected.

----------------------------
 Version 0.02g ---- 3/23/09 
----------------------------
1. Increase Scratch Pad size from 12K to 28K bytes.

   Increase Scratch Pad size from 12K to 28K bytes.  
   Early FPGA build has only 12K bytes.  
   Current FPGA build has 28K bytes Scratch Pad memory which matches with the actual device Scratch Pad memory size.


----------------------------
 Version 0.01g ---- 3/6/09 
----------------------------
1. Initial engineering release

   This release is for 5717 emulation.




